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#%#$$ , 64-bit / 66 mhz master/target pci controller (automatically backwards compatible to 33 mhz or/and 32-bits) , 75 mhz pci interface supported for embedded systems , pci specification v2.2 compliance , programmable back-end interface with three 64-bit busses/100 mhz , provides full 533 mb/s pci data transfer rates (600 mb/s at 75 mhz) '"*%
" - , dma chaining mode for queued dma transactions , four-channel dma mastering, plus a spci (single pci access) mode , unlimited bursts supported in master and target mode , two master write fifos and two master read fifos, each 64-deep and 64 bits wide , target read and write fifos for pre-fetched reads and multipleposted writes , programmable interrupt controller , i2o compliant under microprocessor control , 16 mailbox registers for message passing and semaphores , extended configuration space allowing messaged interrupts, power management, and future pci enhancement support .!$/-$. $%" #%+ $ , supports processor-less systems, as well as 0 wait-state burst connections to all known 8/16/32/64 bit processors , includes non-volatile on-chip configuration data for total customization , independent pci bus (66 mhz) and local bus (100 mhz) clocks , all local interface, control, and glue-logic can be implemented on chip , ?pci friendly? pinout simplifies board layout, supports 4-layer pci boards '"*%
"'- , programmable dma channel arbitration scheme , spci (single pci access) mode may initiate any pci master command , dma controller configurable via pci or back-end , dma chaining mode allows a linked list of dma transfers to occur without user intervention +#!%
, write posting fifo increases performance with queued transactions (up to 16 queued writes) , any bar can be defined as pre-fetchable , six base address registers supported, configurable as memory or io , unique ?target blast mode? enables high- performance and very low overhead streaming data to/from pci

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#%$ / , support for configuration space from 0x40 to 0x3ff , pci expanded capabilities support , expansion rom supported with back-end memory , power management support , compact pci hot-swap/hot-plug compliant , messaged interrupts , configuration specified with anti-fuses on board, external eeprom not needed #!!$#
, 192 programmable i/o pins in a 456 pin or 484 pin pbga package , 74k gates with 11 blocks (total of 12,672 bits) of dual-port ram , 250 mhz 16-bit counters, 275 mhz datapaths, 160 mhz fifos , all back-end interface and glue-logic can be implemented on chip figure 1: ql5064 block diagram 12k bits dual port ram programmable logic pci controller 100 mhz interface 64 64 64 3 recv fifos 64 deep 3 xmit fifos 64 deep 4 channel dma ctrl interrupts messaging config. 192 user i/o pci bus - 33/66/75 mhz 32/64 bits (data and address) high speed logic cells 74k gates

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2** the ql5064 device in the quicklogic quickpci esp (embedded standard products) family provides a complete and customizable pci interface solution combined with 74,000 system gates of programmable logic. this device eliminates any need for the designer to worry about pci bus compliance, yet allows for the maximum possible pci bus bandwidth. the programmable logic portion of the device is built from 792 quicklogic logic cells, and 11 quicklogic dual-port ram blocks. the configurable ram blocks can each operate in 64x18, 128x9, 256x4, or 512x2 mode. these dual-port ram blocks can be cascaded to achieve deeper or wider configurations. they can also be combined with logic cells to form fifos. see the ram section of this data sheet for more information. the ql5064 device includes a complete pre-designed pci initiator/target interface offering full burst mode transfers at 32 or 64 bits per clock cycle. at 66 mhz, this device offers support for 533 mbytes/sec data transfer rates (66.6 mhz * 8 bytes per transfer). at the maximum speed of 75 mhz (exceeding the current maximum speed specification for pci), the ql5064 device can achieve 600 mbytes/sec data transfer rates. the pci interface is configured via internal programmable configuration bits, so no external eeprom or memory is needed. the ql5064 device meets pci 2.2 electrical and timing specifications and has been fully hardware- tested. this device also supports the win ? 98 and pc ? 98 standards. the ql5064 device features 3.3- volt operation with multi-volt compatible i/os. thus it can easily operate in 3.3-volt only systems, as well as mixed 3.3 volt/5 volt system. it can be placed on a universal signaling pci board. a wide range of additional features complements the ql5064 device. the fpga side of the device is 5 volt and 3.3-volt pci-compliant and is capable of implementing fifos at 160 mhz, and counters at over 250 mhz. i/o pins provide individually controlled output enables, dedicated input/feedback registers, and full jtag capability for boundary scan and test. in addition, the ql5064 device provides the benefits of non-volatility, high design security, immediate functionality on power-up, and a self- contained single chip solution.

figure 2: ql5064 device block diagram registers 72x64 dma/ chain xmit0 fifo pci 33/66/75 mhz 32/64 bits (data and add ress ) 72x32 target write/ post fifo 64x16 target read/ prefetch fifo target interface controller configuration pci interface buffers & logic 72x64 dma xmit1 fifo 72x64 dma/ chain rcv0 fifo 72x64 dma rcv1 fifo lane steering pci/fpga interrupt controller data construction data_out interface data_in interface 5 dma controllers chain control xmit0 xmit1 rcv0 rcv1 internal bus arbiter pci to fpga mailbox (8x8) fpga to pci mailbox (8x8) i 2 o messaging control interface 64 64 address latch/ decode/ increment 33 64 pci clock 64 user clock (0-100mhz) control bus decode dq lane steering fpga (792 logic modules) antifuse configuration user i/o (192) 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits 1152 bits embedded memory embedded memory global clk's (4) array clk's (2) single pci access dq user_clk (global clock)

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#% the ql5064 device supports maximum pci transfer rates, so many applications exist which are ideally suited to the device's high performance. high speed data communications, telecommunications, and computing systems are just a few of the broad range of applications areas that can benefit from the high speed pci interface and programmable logic. the pci interface can also act as a pci host controller. this can be accomplished by glue-less interface to most popular 8/16/32/64-bit microprocessors. ) .--2+#%
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the pci interface includes the following 6 fifo buffers: , 2 64x64 pci master transmit buffers , 2 64x64 pci master receive buffers , 1 16x64 pci target read/pre-fetch buffer , 1 32x64 pci target write/post buffer all fifo buffers are 72 bits wide (64 data bits + 8-bit byte enables). pci initiator-mode buffers are 64 deep and support sustained burst transfers. pci target mode buffers are provided for both read and write operations to the pci target, supporting pre-fetched reads with configurable registers. all fifos can operate with independent read and write clocks, so that the programmable logic design can interface to the fifos at up to 100 mhz (a clock asynchronous to the 33/66 mhz pci clock). all data synchronization is accomplished in the pci core. the transmit fifos have full flags and the receive fifos have empty flags. both types of fifos have programmable status flags that may be used to determine if either of the transmit fifos are almost full or if either of the receive fifos are almost empty.

)'-2** each master-mode fifo has its own dma controller to support maximum data throughput. combining one initiator-mode transmit fifo with one initiator-mode receive fifo also supports dma chaining. this unique and flexible dma chaining mode permits a 'linked-list' of transfers to be completed by the dma controller without software or processor intervention. dma registers are accessible by the fpga (back-end interface), as well as the pci bus. dma chaining descriptors are made of 4 64-bit quad-words, or 32 bytes of data per descriptor. each descriptor defines a dma transaction (memory start location, size, read/write) as well as 88 bits of user- defined information (such as a descriptor identifier, or back-end address). dma chaining is a powerful dma feature, allowing the ql5064 device to drive continuous pre-defined dma transactions with no processor or software interaction. single pci access (spci) reads and writes are supported for single quad-word transfers that do not require fifos. spci supports io reads and writes, configuration reads and writes, special cycles, interrupt acknowledge cycles, as well as standard memory read/write transactions. figure 3: dma chaining descriptor user defined (63:0) (local address) first pci address transfer count (bytes) (31:0) user defined (23:0) next descriptor pointer address (63:0) 63 0 offset 0 x 00 0 x 08 0 x 10 0 x 18 r i w c o e 7 0

) $#.& %" 1 2 the pci interface contains 16 bytes of mailbox registers to support message/semaphore passing between the programmable logic design and the pci bus. these mailbox registers are memory mapped to a dedicated register bank within the first 256 bytes of bar 0. 8 bytes are provided for the fpga to pci direction, and 8 bytes are also provided for the pci to fpga direction. status flags and interrupts are available for each direction as well. figure 4 below shows the mailbox structure within the ql5064 device. hardware controlled queues allow full i 2 o messaging support with a processor and local i 2 o drivers. figure 4: mailbox structure full interrupt empty interrupt 63 0 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 63 0 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 status register interrupt control interrupt configuration register interrupt control 8 empty interrupt pci bus cntl bus status register status 8 outgoing decode control incoming decode control status status status full interrupt mailbox 7 mailbox 5 mailbox 3 mailbox 1 mailbox 6 mailbox 4 mailbox 2 mailbox 0 user outgoing mailboxes interrupt configuration register

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the internal interface between the pci controller and the fpga logic cells is both simple and flexible. the interface is configurable, based on the needs of the fpga design. configuration is accomplished at the time of programming the fpga. the fpga/pci interface supports very high bandwidth data transfers via 3 64-bit busses. the interface is totally synchronous, and supports a separate clock from the pci clock. the interface clock can run at up to 100 mhz. these busses are called datain, dataout, and control_data. the datain bus is for moving data from the pci bus to the back-end. the dataout bus is for moving data from the back-end to the pci bus. the control_data bus is for both of the above, and for accessing internal control registers. all 3 busses can operate at 0 wait states, and all can operate at the same time. 6) $#
% all bus accesses to the ql5064 from the fpga (back-end) interface are synchronous to the back-end user clock - called user_clk. this clock is supplied on a dedicated external pin. the pci clock may be routed out to a pin, and then back into the device to be used as the user_clk if desired. the user_clk signal may be asynchronous to the pci_clk signal, and may run at up to 100 mhz with no pll requirements. all busses on the back-end of the ql5064 device can sustain data movement on every cycle of user_clk. figure 5: fpga to pci synchronization pci fpga pci_clk user_clk pci fpga user_clk or osc user_clk

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0 #% the datain bus is used to transfer data from the pci bus to the back-end interface. this data can come from three different data paths: one of the two dma receive fifos, or the target write/post fifo. for proper data management, empty and almost empty flags from the two dma receive fifos are available to the back-end design. the almost empty flags are fully configurable via the control_data bus interface or the pci bus. interface to the target write/post fifo is accomplished through the target interface signals. a block diagram of the datain and target control connections is seen in figure 6. data is transferred to the datain bus in the same byte lane in which is was transferred over the pci bus. to assist with re-aligning or compacting data in the back-end interface, a byte-lane barrel shifter provides the means to manipulate byte lane positioning. this is accomplished with the byte_select[2:0] input. see the datain bus section of the internal signal descriptions for more information. figure 6: datain bus description pci cbe [7:0] pci data datain [63:0] datain_bytesel [2:0] rcv0_fifo_program_empty_flag rcv0_fifo_ef datain_be[7:0] datain_byteid [1:0] rcv1_fifo_program_empty_flag rcv1_fifo_ef datain_src_sel[1:0] datain_cs user_clk fpga target/ write post fifo (32 deep) dma rcv 1 or target write post fifo (64 deep) dma rcv 0 fifo (64 deep) chain descriptor tags byte lane [7:0] byte lane [7:0] byte lane [7:0] lane barrel shifter shifter decode 0 1 2 3 0 1 2 0 1 2 3 64 8 64 8 64 8 64 64 3 8 2 2 2 dq dq dq pci bus

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0 #% the dataout bus is used to transfer data from the back-end interface to the pci bus. this bus is connected to three destinations within the ql5064 device: one of the two dma transmit fifos, or the target read/pre-fetch fifo. for proper data management and high data throughput, full and almost full flags are available for each of the two dma transmit fifos. the almost full flags are fully configurable via the control_data bus interface or the pci bus. interface to the target read/pre-fetch fifo is accomplished through the target interface signals. a block diagram of the dataout connections can be seen in figure 7. the data_outdes[1:0] signals select a particular fifo to be connected to the dataout bus. a block diagram of the dataout bus and its connections can be seen in figure 7. data written to the dma transmit fifos or the target read/pre-fetch fifo must be set up in the same byte lanes in which the data will be transferred in the pci bus. to aid with aligning, re-aligning, or compacting data that is to be written to the fifos via the dataout bus, a byte-lane barrel shifter is present, controlled by the data_out_shift[2:0] signals. see the dataout bus section of the internal signal descriptions table for more information. figure 7: dataout and control bus description fifo 0 transmit control bus interface data_out lane shifter & construction fifo 1 transmit target read fifo to master controller to target controller 0 1 0 1 0 1 0 1 0 1 0 1 wr wr wr 0 1 0 1 0 1 (cntl_addr == 0xc0 ) * ctrl_cs (cntl_addr == 0xc8 ) * ctrl_cs (cntl_addr == 0xf8) * ctrl_cs cntl_data[63:0] byte_lane [7:0] data_out_h [63:0] data_out_beh[7:0] cntl_data_out [63:0] cntl_data_in [63:0] data_out [63:0] data_outdes[1:0] data_outcs user_clk data_out_be[7:0] data_out_byte_sel[2:0] fpga_reset user_clk fpga pci core cntl_wrt_nrd cntl_be[7:0] cntl_addr [7:3] cntl_cs 2 detailed in figure 3?17

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0 #% the control_data bus is the heart of the control circuitry for the pci interface. the intent of this bus is to provide access to all of the control structures necessary for a microprocessor interfaced to the ql5064 device to be able to marshal all pci operations. this bus, like the datain and dataout busses is synchronous to user_clk, and can be written or read on every clock. this is a bi-directional bus, offering both read and write access at 64-bits. in addition to all control structures, this bus is designed to access all of the six fifos. (1) ' #% five possible masters could be driving pci master transactions on the pci bus, and as a result, a flexible arbitration controller has been included in the ql5064 device. the five sources for pci master transactions include: transmit fifo 0, transmit fifo 1, receive fifo 0, receive fifo 1, and spci (single pci access). (spci is a means for the back end-design to initiate single quad-word transfers directly on the pci bus for master transactions, bypassing the dma fifos). spci mastering is controlled through the control_data bus. three arbitration modes have been defined for the ql5064 device. these are round robin, prioritized, and customized. in all modes, the spci mastering always has highest priority. the arbitration scheme is selected by setting the proper values in the arbitration mode bits of configuration registers (offset 0xd0, bits 49:48). the selection is: 00b - round robin, 01b - prioritized, 10b - customized, 11b - reserved. round robin arbitration simply cycles through the four master fifos in the following order: transmit 0 (t0), transmit 1 (t1), receive 0 (r0), receive 1 (r1). prioritized mode uses values assigned to dma_arbitration_priority bits in the configuration memory (offset 0xd0). masters set to equal priority are arbitrated (high to low): t0, t1, r0, r1. customized arbitration mode uses two busses and back-end logic. the fpga_bus_req[3:0] signals (1 bit per fifo) indicate to the programmable logic design which master is requesting the bus. the fpga_bus_req bits are assigned: [0]-r1, [1]-r0, [2]-t1, [3]-t0. the back-end design should set fpga_arb_sel[1:0] according to which master should be granted the bus. the fpga_arb_sel bus uses the enumeration: 00-r1, 01-r0, 10-t1, 11-t0.

(3) #%#$& dma control and ql5064 registers can be accessed from the pci bus or the back-end control_data bus. on the pci side, these registers are accessed off of bar 0, with offets 0x00 to 0xff (below 0x100). the breakdown of this memory space can be seen in the following table. receive fifo0[63:0] (r only) receive fifo1[63:0] (r only) transmit fifo0[63:0] (w only) transmit fifo1[63:0] (w only) reserved target control address[63:0] (r only) target control data[63:0] (r/w) 80 88 90 98 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 single pci access address register[63:0] (r/w) single pci access data register[63:0] (r/w) user incoming mb full interrupt mask[7:0] reserved 0000_0000 0 bist code[3:0] dma cancel max retry [1:0] lat en fifo thresh to[1:0] user outgoing mb empty [7:0] user incoming mb full [7:0] xmt1 rcv0 rcv1 chn b i s t xmt0 dma interrupt i 2 o status user outgoing mb empty interrupt mask[7:0] error xmt1 rcv0 rcv1 chn xmt0 r ta p e d mr t ma i 2 o interrupt ifle iplf xmt1 rcv0 rcv1 xmt0 dma start/done# chn user incoming mb status [7:0] user outgoing mb status [7:0] b i d o xmt1 rcv0 rcv1 xmt0 fifo flush xmt1 xmt0 000 0000 dma 32/64# xmt1 rcv0 rcv1 xmt0 dma arbitration priority xmt1[1:0] rcv0[1:0] rcv1[1:0] xmt0[1:0] 0000 0000_00 arb mode [1:0] reserved b i s t ce chain ptr fetch end spci 0000_0000 i 2 o int mask 0000_0000 0000 00 s p i 0000 0 0000 0000 b i ms dma interrupt mask xmt1 rcv0 rcv1 xmt0 chn ce s p ma user_be_req[7:0] user region [2:0] 0 tu m tav tu r tu r w 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4 2 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 be en [1:0] 0 chn reserved 0000_0000 0000_0000 0000_0000 0000_0000 dma spc rcv1 rcv0 000 oflf ople ifle iplf oflf ople ifle iplf oflf ople pci incoming mb empty interrupt mask[7:0] pci outgoing mb empty interrupt mask[7:0] xmt1 xmt0 master write address 0[63:0] (r/w) master write count status0[31:0] (r only) master write transfer count0[31:0] (r/w) master write address 1[63:0] (r/w) master write count status1[31:0] (r only) master write transfer count1[31:0] (r/w) reserved 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 user id [7:0] (r only) antifuse receive fifo 0 byte lane[7:0] receive fifo 1 byte lane[7:0] chip revision id [7:0] (r only) master read address 0[63:0] (r/w) / chain descriptor start address [63:0] (r/w) master read count status0[31:0] (r only) master read transfer count0[31:0] (r/w) master read address 1[63:0] (r/w) master read count status1[31:0] (r only) master read transfer count1[31:0] (r/w) user incoming mail 0 user incoming mail 1 user incoming mail 6 user incoming mail 5 user incoming mail 4 user incoming mail 2 user incoming mail 3 user incoming mail 7 user outgoing mail 0 user outgoing mail 1 user outgoing mail 6 user outgoing mail 5 user outgoing mail 4 user outgoing mail 2 user outgoing mail 3 user outgoing mail 7 i 2 o interrupt mask bit [3] i 2 o interrupt service request bit [3] i 2 o outbound queue pointer i 2 o inbound queue pointer r o tag0 [1:0] r c e r c a e x m a f x m f x m a f x m f r c e single pci access bus request byte lanes[7:0] cmd[3:0] strt target burst request bar[5:0] 0 r o target prefetch cntl bar[5:0] 0 r c a e target fifo control -- emptyness threshold bar0 bar1 bar2 bar3 bar4 bar5 target fifo threshold msb's[3:0] target bar configuration (r only) bar0 bar1 bar2 bar3 bar4 bar5 0 00 bar enable (r only) 4 3 2 1 5 32 bit rom wwt wrt en 16 /8 0000 receive fifo0 almost full[5:0] (r/w) 00 receive fifo1 almost full[5:0] (r/w) xmit fifo 0 almost full[5:0] (r/w) 00 00 xmit fifo 1 almost full[5:0] (r/w) 00 receive fifo0 almost empty[5:0] (r/w) 00 receive fifo1 almost empty[5:0] (r/w) xmit fifo 0 almost empty[5:0] (r/w) 00 00 xmit fifo 1 almost empty[5:0] (r/w) 00 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4 2 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipeline not empty xmt 0 xmt 1 xmt 0 xmt 1 rcv 0 rcv 1 user memory map

()&'#"$- figure 8: ram module the ram modules are "dual-ported", with completely independent read and write ports and separate read and write clocks. the read ports support asynchronous and synchronous operation, while the write ports support synchronous operation. each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read operation (asyncrd input low), or as a flow-through enable for asynchronous read operation (asyncrd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. this approach allows up to 512-deep configurations as large as 22 bits wide in the ql5064 device. a similar technique can be used to create depths greater than 512 words. in this case address signals higher than the eighth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher read address bits for the multiplexer select signals. mode[1:0] wa[a:0] wd[w:0] we wclk ram module asyncrd ra[a:0] rd[w:0] re rclk mode: 64x18 128x9 256x4 512x2 address busses [a:0] [5:0] [6:0] [7:0] [8:0] data busses [w:0] [17:0] [8:0] [3:0] [1:0]

figure 9: quickworks tool suite ();'<00# jtag pins support ieee standard 1149.1a to provide boundary scan capability for ql5064 devices. six pins are dedicated to jtag and programming functions on each ql5064 device, and are unavailable for general design input and output signals. tdi, tdo, tck, tms, and trstb are jtag pins. a sixth pin, stm, is used only for programming. ()*$#0!%##$00# software support for the ql5064 device is available through the quickworks development package. this turnkey pc-based quickworks package, shown in figure 9, provides a complete esp software solution with design entry, logic synthesis, place and route, and simulation. quickworks includes vhdl, verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated synplicity synplify lite tool, specially tuned to take advantage of the ql5064 architecture. quickworks also provides functional and timing simulation for guaranteed timing and source-level debugging. the unix-based quicktools ? and pc-based quickworks-lite packages are a subset of quickworks and provide a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. quicktools and quickworks-lite read edif netlists and provide support for all quicklogic devices. quicktools and quickworks-lite also support a wide range of third-party modeling and simulation tools. in addition, the pc-based package combines all the features of quickworks-lite with the scs schematic capture environment, providing a low-cost design entry and compilation solution. schematic schematic turbo writer hdl editor third party design entry & synthesis third party simulation vhdl/ vhdl/ verilog verilog scs schematic tools silos simulators quick tools /quick chip : optimize, place, & route mixed-mode design mixed-mode design synplify-lite hdl synthesis quick works design software &

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the ql5064 device is designed to be highly customizable. this diagram illustrates the interface signals present between the configurable pci core, and the programmable logic region of the ql5064 device. detailed descriptions of each of these interface signals follow in the next section. figure 10: pci to programmable logic interface block diagram pci block programmable logic and dual-port ram pci_clk_2fpga user_clk fpga_reset user_stop user_req user_be_req[7:0] user_addr_valid addr_select user_addr_output[32:0] datain_bytesel[2:0] datain[63:0] datain_be[7:0] datain_src_sel[1:0] datain_cs rcv0_fifo_ef rcv0_fifo_prog_empty_flag rcv1_fifo_ef rcv1_fifo_prog_empty_flag xmt0_fifo_ff xmt0_fifo_prog_full_flag xmt1_fifo_ff xmt1_fifo_prog_full_flag cntl_data_in[63:0] cntl_data_out[63:0] cntl_wrt_nrd cntl_addr[7:3] cntl_be[7:0] cntl_cs data_out[63:0] data_outcs data_outdes[1:0] data_outbe[7:0] interrupt_o interrupt_i ad[63:0] c/be[7:0] pa r frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# par64 req64# ack64# inta# user i/o (192) user_region[2:0] datain_byteid[1:0] user_mult user_rdwr spci_done tdi tdo tck tms trst# fpga_loc_sel[1:0] fpga_bus_req[3:0] data_out_byte_sel[2:0] gclk (4) aclk (2) user_clk

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defaults for most configuration space parameters can be programmed into the via-link antifuse based configuration region in the device. also, by fully supporting the extended configuration space region beyond the 40(hex), the full enhanced feature set of the pci bus is available to the user. figure 11: configuration space block diagram device id vendor id status command class code revision id bist base address registers header type latency timer cashe line size subsystem id subsystem vendor id cardbus cis pointer reserved cap. ptr expansion rom base address reserved max_lat min_gnt interrupt pin interrupt line fpga controlled using barcs[7] 31 16 15 0 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch 40h ff r af m af rw r af r af rw r af m af r af rw m af m af m af m af m af m af r af r af r af r af r af m af r af r af r af r af r af m af rw legend read only antifuse program read / write masked by antifuses read / write rw

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@3)3?a'@1b =c@()> the ac specifications, logic cell diagrams and waveforms are provided below. to calculate delays, multiply the appropriate k factor in the ? operating range ? section by the following numbers. figure 12: quickpci logic cell configuration ( e
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figure 13: static idd of the ql5064 9 -$ e)& /!#$ ! #%" #% % . 9% ? %0<?#$ )? ? 2f) ? ie e 3i
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1)2" %%+#! #% ql 5064 - 66b pb456 c quicklogic device quickpci device part number speed grade 33a = quick 33b = fast 66a = faster 66b = super fast 75c = fastest op era ti ng ra nge c = commercial i = industrial package code pb 456 = 456-p in pbg a ps484 = 484- pin pbg a

1) %5<' %# ! figure 14: 456 pin pbga pinout diagram ql5064-66-bpb456c quickpci bottom view top view pin a1 corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ql5064-66bpb456c quickpci bottom view top view pin a1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af

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-082 8 f>- u5 -0982 !(5 f - f #(9 > ( -0b2 9 f>- u8 -09(2 !(8 f -( f #(= f 5 -0(2 = f>- u9 > !(9 f -5 f -0852 8 -012 (( >- u(( >- !(= f -8 f ( -05c2 9 > (5 f u(5 f > -9 f 5 -0592 f>- (8 f u(8 f ( > -= f 8 -0552 ( f>- (9 f u(9 f 5 > -: f 9 -05(2 5 f>- (= f u(= f 8 >- -b f = -0582 8 f>- ? > -0952 9 -08b2 -c f : e 9 f>- ?( !#>0=2 ( -092 = > -(1 f b > = f>- ?5 7=8 5 -0912 : > -( f c > (( f ?8 -0=(2 8 > b i -(( f 1 f (5 ekf ?9 >- 9 i c > -(5 7%! f (8 ekf ?(( f (( i 1 > -(8 f ( f (9 f ?(5 f (5 > f -(9 f 5 f (= ekf ?(8 f (8 f ( f -(= > 8 f 7 -0:2 ?(9 f (9 f 5 f # - 9 f 7( -092 ?(= f (= f 8 i #( -082 = f 75 7#d=8> i !#>082 ! -08c2 9 f #5 -05:2 : f 78 > i( -0=52 !( -08:2 = f #8 -08(2 b f 79 > i5 -0=12 !5 > : f #9 -0812 c f 7 f>- i8 > !8 > b f #= -05=2 (1 f 7( f>- i9 > !9 >- c f #: > ( f 75 f>- i(( >- != i (1 f #b e (( f 78 f>- i(5 f !: > ( f #c > (5 f 79 f>- i(8 f !b > (( f #1 > (8 f 7= f>- i(9 f !c > (5 >- # f (9 f 7(( i i(= f !1 i (8 f #( f (= f c 89=! @ $a % -%
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14)6 %5<' %# ! figure 15: 484 pin pbga pinout diagram ql5064-66-bpb456c quickpci bottom view top view pin a1 corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ql5064-66bps484c quickpci bottom view top view pin a1 corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab

16)6 %5<' %#$ (1 8b8! % -%
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#% 1 > !c f -9 f f /: i k5 7.#> 1( > !(1 k -= f ( f /b $ k8 % > 15 -0(c2 !( > -: > 5 $ /c i k9 7-u> 18 -0(:2 !(( > -b > 8 f /1 i k= i 19 -0512 -0(2 -c %. 9 $ / f k: i 1= -%#e ( > -(1 f = i /( $ kb $ 1: -0(=2 5 > -( f : f /5 > kc $ 1b e 8 > -(( f b f /8 i k1 $ 1c f 9 -052 # #77> c f /9 $ k $ 1 f = >> #( -092 (1 f /= f k( $ f : > #5 -0(92 ( f /: f k5 $ ( f b i #8 -0(52 (( f /b f k8 $ 5 f c f #9 > !#>02 /c > k9 $ 8 f 1 f #= i ( -052 /(1 f k= f 9 f f #: -0(12 5 > /( f k: f = f ( f #b -0(b2 8 %#77> /(( f kb f : f 5 f #c e 9 $ t -0c2 kc f b f 8 f #1 f = i t( !#>012 k(1 f c f 9 f # i : $ t5 > k( f (1 f = f #( f b >> t8 -012 k(( f (>:f #5f c$t9$e-0=2 (( > b f #8 f 1 f t= $ e( ek ! > c f #9 f $ t: $ e5 ek !( > (1 f #= f ( > tb i e8 > !5 - ( f #: i 5 f tc $ e9 ek !8 -0=2 (( f #b i 8 $ t1 $ e= k=8> !9 7#d> - !#>0(2 #c f 9 $ t $ e: $ != -0b2 -( 7 #(1 f = $ t( $ eb i !: -0((2 -5 -0c2 #( f : f t5 $ ec $ !b 7%> -8 !#>052 #(( f b f t8 $ e1 $ !c i -9 > -#i%#e> c f t9 i e $ !1 f -= > ( > (1 f t= $ e( $ ! f -: -0(82 5 -0:2 ( f t: f e5 $ !( f -b > 8 > (( f tb f e8 $ !5 f -c e 9 > / -0(2 tc > e9 i !8 f -1 > = $ /( > t(1 f e= $ !9 f - f : i /5 -02 t( f e: f != f -( f b $ /8 > t(( f eb f !: f -5 > c $ /9 i k 7-u> ec f !b f -8 f 1 $ /= -082 k( > e(1 f =(#+1>

e( f >b f 79 $ ?( f 3c f = -08b2 e(( f >c > 7= i ?5 f 31 f : > . -082 >(1 f 7: i ?8 f 3 f b > .( > >( f 7b f ?9 $ 3( f c e .5 -0(2 >(( f 7c f ?= f 35 f 1 f .8 -012 -02 7(1 f ?: $ 38 f f .9 ek ( -052 7( f ?b i 39 f ( f .= $ 5 > 7(( f ?c f 3= f 5 f .: $ 8 !#>0=2 !#>082 ?(1 f 3: > 8 f .b i 9 $ ( -0=12 ?( f 3b > 9 f .c $ = i 5 > ?(( f 3c > = f .1 $ : $ 8 -09c2 i -0992 3(1 f : f . $ b $ 9 $ i( -09=2 3( f b f .( $ c $ = -0=(2 i5 > 3(( f c .% .5 $ 1 $ : $ i8 -08:2 u -09(2 (1 f .8 $ $ b $ i9 i u( -08c2 ( > .9 i ( $ c $ i= -0812 u5 > (( > .= $ 5 $ 1 f i: -05=2 u8 > ! > .: ekf 8 $ $ ib e u9 -082 !( > .b ekf 9 $ ( f ic f u= -05:2 !5 - .c > = $ 5 f i1 f u: -05b2 !8 -0852 .(1 ekf @?%#7eka : f 8 f i i ub -0582 !9 -08=2 .( ekf b f 9 f i( f uc e != -08(2 .(( f c f = $ i5 f u1 f !: -0552 > -0b2 (1 f : f i8 f u f !b -05(2 >( > ( f b f i9 f u( f !c i >5 -0:2 (( f c > i= f u5 f !1 f >8 -092 7 !#>0:2 (1 f i: i u8 f ! f >9 i 7( > ( f ib f u9 f !( f >= 7#d=8> 75 !#>092 (( f ic f u= f !5 f >: i 78 > ? -0=2 i(1 f u: f !8 f >b $ 79 -0=52 ?( -09b2 i( f ub f !9 f >c $ 7= 7=8 ?5 -0952 i(( f uc f != f >1 $ 7: > ?8 > 3 -0982 u(1 > !: f > $ 7b $ ?9 -09:2 3( -092 u( f !b f >( $ 7c i ?= $ 35 -0912 u(( f !c 7%! >5 $ 71 f ?: i 38 > > !(1 f >8 $ 7 > ?b i 39 > ( > !( > >9 $ 7( $ ?c f 3= -0882 5 -0892 !(( > >= f 75 f ?1 f 3: > 8 -05c2 >: f 78 i ? f 3b > 9 -0592 (1 8b8! @ $a % -%
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17)&* #% #/ copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this product brief, and the accompanying software programs are protected by copyright. all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic, pasic, and vialink are registered trademarks, and spde and quick works are trademarks of quicklogic corporation. verilog is a registered trademark of cadence design systems, inc. ( 7)& /& + &* #% #!!% %ccc && ! .*(11 ?$ && -(11 7" $$"
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